Serial communication receivers are used in integrated circuits, such as application specific integrated circuits (ASICs), for clock synchronization and for recovery of serial data streams from transmission channels. Clock signals and data are recovered by detecting the data and transitions in the serial data stream. The voltage levels of data bits (or symbols) within such serial data stream may be depicted in an “eye diagram” in which a view of multiple waveforms of such data bits are superimposed upon each other. The time and voltage ranges of the data within each cycle in the stream are known as the data “eye.” The serial data stream is preferably sampled at or near the center of this eye. Unfortunately, transmission channels normally used in serial links exhibit low-pass and other filter effects that distort transmitted signals which may result in closure of the data eyes and consequent transmission errors. Using a technique known as “receive equalization,” or simply “equalization,” serial receivers boost their voltage sensitivity at the attenuated frequencies to flatten the frequency response of the combined transmitter, communication channel, and receiver (collectively, the “link”).